首頁 >MM74HC173MX>規(guī)格書列表
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QuadD-typeflip-flop;positive-edgetrigger;3-state GENERALDESCRIPTION The74HC/HCT173arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT173are4-bitparallelloadregisterswithclockenablecontrol,3-statebufferedoutputs( | PhilipsPhilips Semiconductors 飛利浦荷蘭皇家飛利浦 | Philips | ||
QuadD-typeflip-flop;positive-edgetrigger;3-state 1.Generaldescription The74HC173;74HCT173isaquadpositive-edgetriggeredD-typeflip-flop.Thedevicefeatures clock(CP),masterreset(MR),twoinputenable(E1,E2)andtwooutputenable(OE1,OE2)inputs. WhentheinputenablesareLOW,theoutputsQnwillassumethestateoftheirco | NEXPERIANexperia B.V. All rights reserved 安世安世半導(dǎo)體(中國)有限公司 | NEXPERIA | ||
QuadD-typeflip-flop;positive-edgetrigger;3-state GENERALDESCRIPTION The74HC/HCT173arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT173are4-bitparallelloadregisterswithclockenablecontrol,3-statebufferedoutputs( | PhilipsPhilips Semiconductors 飛利浦荷蘭皇家飛利浦 | Philips | ||
QuadD-typeflip-flop;positive-edgetrigger;3-state 1.Generaldescription The74HC173;74HCT173isaquadpositive-edgetriggeredD-typeflip-flop.Thedevicefeatures clock(CP),masterreset(MR),twoinputenable(E1,E2)andtwooutputenable(OE1,OE2)inputs. WhentheinputenablesareLOW,theoutputsQnwillassumethestateoftheirco | NEXPERIANexperia B.V. All rights reserved 安世安世半導(dǎo)體(中國)有限公司 | NEXPERIA | ||
QuadD-typeflip-flop;positive-edgetrigger;3-state GENERALDESCRIPTION The74HC/HCT173arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT173are4-bitparallelloadregisterswithclockenablecontrol,3-statebufferedoutputs( | PhilipsPhilips Semiconductors 飛利浦荷蘭皇家飛利浦 | Philips | ||
QuadD-typeflip-flop;positive-edgetrigger;3-state 1.Generaldescription The74HC173;74HCT173isaquadpositive-edgetriggeredD-typeflip-flop.Thedevicefeatures clock(CP),masterreset(MR),twoinputenable(E1,E2)andtwooutputenable(OE1,OE2)inputs. WhentheinputenablesareLOW,theoutputsQnwillassumethestateoftheirco | NEXPERIANexperia B.V. All rights reserved 安世安世半導(dǎo)體(中國)有限公司 | NEXPERIA | ||
HighSpeedCMOSLogicQuadD-TypeFlip-Flop,Three-State | TITexas Instruments 德州儀器美國德州儀器公司 | TI | ||
High-SpeedCMOSLogicQuadD-TypeFlip-Flop,Three-State | TITexas Instruments 德州儀器美國德州儀器公司 | TI | ||
High-SpeedCMOSLogicQuadD-TypeFlip-Flop,Three-State | TITexas Instruments 德州儀器美國德州儀器公司 | TI | ||
High-SpeedCMOSLogicQuadD-TypeFlip-Flop,Three-State | TITexas Instruments 德州儀器美國德州儀器公司 | TI |
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