ZL30110

PDH/SDH System Synchronizer; Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz\nProvides DPLL lock and reference fail indication\nAutomatic free run mode on reference fail\nDPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference\nLess than 5 psecrmson 25 MHz outputs, and less than 0.6 nsppintrinsic jitter on the all other outputs\nMinimal input to output and output to output skew\n25 MHz external master clock source: clock oscillator or crystal\nSimple hardware control interface\nProvides a range of output clocks:65.536 MHz TDM clock locked to the input reference\nGeneral purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator\nGeneral purpose 125 MHz and 66 MHz or 100 MHz locked to the external crystal or oscillator;

The ZL30110 clock rate conversion digital phase-locked loop (DPLL) provides accurate and reliable frequency conversion. The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. In the locked mode, the reference input is continuously monitored for a failure condition. In the event of a failure, the DPLL continues to provide a stable free running clock ensuring system reliability.

ZL30110

Telecom Rate Conversion DPLL

ZL30110LDE

Telecom Rate Conversion DPLL

ZL30110LDE1

Telecom Rate Conversion DPLL

ZL30110LDF1

Package：32-VFQFN 裸露焊盤(pán)；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類(lèi)別：集成電路（IC） 應(yīng)用特定時(shí)鐘/定時(shí) 描述：IC DPLL RATE CONVERSION 32QFN

ZL30110LDG1

Package：32-VFQFN 裸露焊盤(pán)；包裝：卷帶（TR） 類(lèi)別：集成電路（IC） 應(yīng)用特定時(shí)鐘/定時(shí) 描述：IC DPLL RATE CONVERSION 32QFN