UPD720102

USB 2.0 HOST CONTROLLER; ? Compliant with universal serial bus specification revision 2.0 (data rate: 1.5/12/480 Mbps)\n? Compliant with open host controller interface specification for USB release 1.0a\n? Compliant with enhanced host controller interface specification for USB revision 1.0\n? PCI multi-function device consists of one OHCI host controller core for full-/low-speed signaling and one EHCI host controller core for high-speed signaling\n? Root hub with 3 (Max.) downstream facing ports which are shared by OHCI and EHCI host controller cores\n? All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction\n? Supports hyper-speed transfer mode using HSMODE signal\n? 32-bit 33 MHz host interface compliant with PCI specification revision 2.2\n? Supports PCI mobile design guide version 1.1\n? Supports PCI-bus power management interface specification revision 1.1\n? PCI bus bus-master access\n? Supports 3.3 V PCI\n? System clock is generated by 30 MHz crystal or 48 MHz clock input\n? Operational registers direct-mapped to PCI memory space\n? 3.3 V single power supply, 1.5 V internal operating voltage from on chip regulator\n? On chip Rs and Rpd resistors for USB signals;

The μPD720102 complies with the universal serial bus specification revision 2.0 and open host controller interface specification for full-/low-speed signaling and Intel's enhanced host controller interface specification for high-speed signaling and works up to 480 Mbps. The μPD720102 is integrated 2 host controller cores with PCI interface and USB 2.0 transceivers into a single chip.FEATURES\n? Compliant with universal serial bus specification revision 2.0 (data rate: 1.5/12/480 Mbps)\n? Compliant with open host controller interface specification for USB release 1.0a\n? Compliant with enhanced host controller interface specification for USB revision 1.0\n? PCI multi-function device consists of one OHCI host controller core for full-/low-speed signaling and one EHCI host controller core for high-speed signaling\n? Root hub with 3 (Max.) downstream facing ports which are shared by OHCI and EHCI host controller cores\n? All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction\n? Supports hyper-speed transfer mode using HSMODE signal\n? 32-bit 33 MHz host interface compliant with PCI specification revision 2.2\n? Supports PCI mobile design guide version 1.1\n? Supports PCI-bus power management interface specification revision 1.1\n? PCI bus bus-master access\n? Supports 3.3 V PCI\n? System clock is generated by 30 MHz crystal or 48 MHz clock input\n? Operational registers direct-mapped to PCI memory space\n? 3.3 V single power supply, 1.5 V internal operating voltage from on chip regulator\n? On chip Rs and Rpd resistors for USB signals

UPD720102

PRELIMINARY PRODUCT BRIEF, USB 2.0 HOST CONTROLLER

UPD720102GC-YEB-A

Package：120-TQFP；包裝：托盤 功能：控制器 類別：集成電路（IC） 控制器 描述：IC HOST CTLR USB2.0 3-PORTS QFP

ETC

TPS720102YZUR

350mA,Ultra-LowVIN,RFLow-DropoutLinearRegulatorWithBiasPin

TPS720102YZUT

350mA,Ultra-LowVIN,RFLow-DropoutLinearRegulatorWithBiasPin