UPD30500A中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

DESCRIPTION

The μPD30500 (VR5000), μPD30500A (VR5000A), and μPD30500BNote (VR5000B) are a high-performance, 64- bit RISC (Reduced Instruction Set Computer) type microprocessors employing the RISC architecture developed by MIPSTM Technologies Inc.

The instructions of the VR5000, VR5000A, and VR5000B are compatible with those of the VR3000TM Series and VR4000TM Series and higher, and completely compatible with those of the VR10000TM. Therefore, present applications can be used as they are.

FEATURES

? Employs 64-bit MIPS-based RISC architecture

? High-speed processing

? 2-way super scalar 5-stage pipeline

? 5.5 SPECint95, 5.5 SPECfp95, 278 MIPS (μPD30500)

6.6 SPECint95, 6.6 SPECfp95, 353 MIPS (μPD30500A)

8 SPECint95, 8 SPECfp95, 423 MIPS (μPD30500B)

? High-speed translation buffer mechanism (TLB) (48 entries)

? Address space Physical: 36 bits, Virtual: 40 bits

? Floating-point unit (FPU)

? Sum-of-products operation instruction supported

? Primary cache memory (instruction/data: 32 Kbytes each)

? Secondary cache controller

? Maximum operating frequency Internal: 200 MHz (μPD30500), 250 MHz (μPD30500A), 300 MHz (μPD30500B)

External: 100 MHz

? Selectable external/internal multiple rate from twice to eight times

? Instruction set compatible with VR3000 and VR4000 Series and higher (conforms to MIPS I, II, III, and IV)

? Supply voltage: 3.3 V ±5 (μPD30500)

Core: 2.5 V ±5, I/O: 3.3 V ±5 (μPD30500A)

Core: 1.8 V ±0.1 V, I/O: 3.3 V ±5 (μPD30500B)

APPLICATIONS

? High-performance embedded systems

? Multimedia systems

? Entry-class computers

? Image processing systems