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TPS62964RPYR中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

TPS62964RPYR
廠商型號(hào)

TPS62964RPYR

功能描述

TPS6296x 3V to 17V, 4.5A/6A/8A, 0.6VREF, Low Noise and Low Ripple Buck Converter With Integrated Ferrite Bead Filter Compensation

絲印標(biāo)識(shí)

T62964

封裝外殼

VQFN-HR

文件大小

1.69542 Mbytes

頁(yè)面數(shù)量

35 頁(yè)

生產(chǎn)廠商 Texas Instruments
企業(yè)簡(jiǎn)稱

TI1德州儀器

中文名稱

美國(guó)德州儀器公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-7-3 18:30:00

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TPS62964RPYR規(guī)格書詳情

1 Features

? Low output 1/f noise < 20μVRMS (100Hz to

100kHz)

? Low output voltage ripple < 10μVRMS after ferrite

bead

? High PSRR of > 65dB (up to 100kHz)

? 1.1MHz, 700kHz, or 500kHz fixed frequency peak

current mode control

? Synchronizable with external clock (optional)

? Integrated loop compensation supports ferrite

bead for second stage L-C filter with 30dB

attenuation (optional)

? Spread spectrum modulation (optional)

? 3.0V to 17V input voltage range

? 0.6V to 5.5V output voltage range

? 25mΩ/7mΩ RDSon

? Output voltage accuracy of ±1% over temperature

? Precise enable input allows

– User-defined undervoltage lockout

– Exact sequencing

? Adjustable soft start

? Power-good output

? Output discharge (optional)

? –40°C to 150°C junction temperature range

? 2.0mm × 3.0mm QFN with 0.5mm pitch

? Create a custom design using the TPS6296x with

the WEBENCH? Power Designer

2 Applications

? Telecom infrastructure

? Test and measurement

? Aerospace and defense (radar, avionics)

? Medical

3 Description

The TPS6296x devices are a family of high-efficiency,

low noise, and low ripple current mode synchronous

buck converters. The devices are designed for noise

sensitive applications that normally use an LDO for

post regulation such as high-speed ADCs, clock

and jitter cleaner, serializer, de-serializer, and radar

applications.

To reduce the output voltage ripple, the device

loop compensation is designed to operate with an

optional second-stage ferrite bead L-C filter. Lowfrequency

noise levels, similar to a low-noise LDO,

are further achieved by filtering the internal voltage

reference with a capacitor connected to the NR/SS

pin. Combined, these features allow for an output

voltage ripple below 10μVRMS.

The device operates at a fixed switching frequency

of 1.1MHz, 700kHz, or 500kHz, and can be

synchronized to an external clock. An optional spread

spectrum modulation scheme spreads the DC/DC

switching frequency over a wider span, which lowers

the mixing spurs.

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