TPIC6596

用于增強(qiáng)級(jí)聯(lián)、具有熱關(guān)斷功能的 8 位移位寄存器; ? Low rDS(on) . . . 1.3 Typ\n? Avalanche Energy . . . 75 mJ\n? Eight Power DMOS Transistor Outputs of 250-mA Continuous Current\n? 1.5-A Pulsed Current Per Output\n? Output Clamp Voltage at 45 V\n? Enhanced Cascading for Multiple Stages\n? All Registers Cleared With Single Input\n? Low Power Consumption;

The TPIC6596 is a monolithic, high-voltage, high-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK) respectively. The storage register transfers data to the output buffer when shift-register clear (SRCLR)\\ is high. When SRCLR\\ is low, all registers in the device are cleared. When output enable (G)\\ is held high, all data in the output buffers is held low and all drain outputs are off. When G\\ is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. Outputs are low-side, open-drain DMOS transistors with output ratings of 45 V and 250-mA continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS-transistor outputs have sink current capability. Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1, 10, 11, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between the logic and load circuits. The TPIC6596 is characterized for operation over the operating case temperature range of -40°C to 125°C.

TPIC6596

POWER LOGIC 8-BIT SHIFT REGISTER

TPIC6596

POWER LOGIC 8-BIT SHIFT REGISTER

TPIC6596_16

POWER LOGIC 8-BIT SHIFT REGISTER

TPIC6596DW

POWER LOGIC 8-BIT SHIFT REGISTER

TPIC6596DWG4

POWER LOGIC 8-BIT SHIFT REGISTER

TPIC6596DWRG4

POWER LOGIC 8-BIT SHIFT REGISTER

TPIC6596N

POWER LOGIC 8-BIT SHIFT REGISTER

TPIC6596N

POWER LOGIC 8-BIT SHIFT REGISTER

TPIC6596DWR

Package：20-SOIC（0.295"，7.50mm 寬）；包裝：卷帶（TR） 功能：串行至并行，串行 類(lèi)別：集成電路（IC） 移位寄存器 描述：IC PWR 8-BIT SHIFT REGIS 20-SOIC