TP2104

P-Channel Enhancement-Mode Vertical DMOS FETs

GeneralDescription Thislowthresholdenhancement-mode(normally-off)transistorutilizesaverticalDMOSstructureandSupertex’swell-provensilicon-gatemanufacturingprocess.Thiscombinationproducesadevicewiththepowerhandlingcapabilitiesofbipolartransistorsandwiththehighin

TP2104

P-Channel Enhancement Mode Vertical DMOS FETs

GeneralDescription Thislowthresholdenhancement-mode(normally-off)transistorutilizesaverticalDMOSstructureandSupertex’swell-provensilicon-gatemanufacturingprocess.Thiscombinationproducesadevicewiththepowerhandlingcapabilitiesofbipolartransistorsandwiththehighin

TP2104

P-Channel Enhancement Mode Vertical DMOS FETs

GeneralDescription Thislowthresholdenhancement-mode(normally-off)transistorutilizesaverticalDMOSstructureandSupertex’swell-provensilicon-gatemanufacturingprocess.Thiscombinationproducesadevicewiththepowerhandlingcapabilitiesofbipolartransistorsandwiththehighin

TP2104

MOSFET, P-Channel Enhancement-Mode, -40V, 6.0 Ohm; High input impedance and high gain \nLow power drive requirement \nEase of paralleling \nLow CISS and fast switching speeds \nExcellent thermal stability \nIntegral source-drain diode \nFree from secondary breakdown;

This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.Vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.

TP2104K1

P-Channel Enhancement-Mode Vertical DMOS FETs; ? Free from secondary breakdown\n? Low power drive requirement\n? Ease of paralleling\n? Low CISS and fast switching speeds\n? Excellent thermal stability\n? Integral Source-Drain diode\n? High input impedance and high gain\n? Complementary N- and P-channel devicesApplications\n? Logic level interfaces – ideal for TTL and CMOS\n? Solid state relays\n? Battery operated systems\n? Photo voltaic drives\n? Analog switches\n? General purpose line drivers\n? Telecom switches;

Advanced DMOS Technology\nThese enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown.\nSupertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.

TP2104K1

P-Channel Enhancement-Mode Vertical DMOS FETs

GeneralDescription Thislowthresholdenhancement-mode(normally-off)transistorutilizesaverticalDMOSstructureandSupertex’swell-provensilicon-gatemanufacturingprocess.Thiscombinationproducesadevicewiththepowerhandlingcapabilitiesofbipolartransistorsandwiththehighin

TP2104K1-G

P-Channel Enhancement Mode Vertical DMOS FETs

GeneralDescription Thislowthresholdenhancement-mode(normally-off)transistorutilizesaverticalDMOSstructureandSupertex’swell-provensilicon-gatemanufacturingprocess.Thiscombinationproducesadevicewiththepowerhandlingcapabilitiesofbipolartransistorsandwiththehighin

TP2104N3

P-Channel Enhancement-Mode Vertical DMOS FETs

GeneralDescription Thislowthresholdenhancement-mode(normally-off)transistorutilizesaverticalDMOSstructureandSupertex’swell-provensilicon-gatemanufacturingprocess.Thiscombinationproducesadevicewiththepowerhandlingcapabilitiesofbipolartransistorsandwiththehighin

TP2104N3

P-Channel Enhancement-Mode Vertical DMOS FETs; ? Free from secondary breakdown\n? Low power drive requirement\n? Ease of paralleling\n? Low CISS and fast switching speeds\n? Excellent thermal stability\n? Integral Source-Drain diode\n? High input impedance and high gain\n? Complementary N- and P-channel devicesApplications\n? Logic level interfaces – ideal for TTL and CMOS\n? Solid state relays\n? Battery operated systems\n? Photo voltaic drives\n? Analog switches\n? General purpose line drivers\n? Telecom switches;

Advanced DMOS Technology\nThese enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown.\nSupertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.

TP2104N3-G

P-Channel Enhancement Mode Vertical DMOS FETs

GeneralDescription Thislowthresholdenhancement-mode(normally-off)transistorutilizesaverticalDMOSstructureandSupertex’swell-provensilicon-gatemanufacturingprocess.Thiscombinationproducesadevicewiththepowerhandlingcapabilitiesofbipolartransistorsandwiththehighin