STM32F479ZG數(shù)據(jù)手冊ST中文資料規(guī)格書

描述 Description

The STM32F479xx devices are based on the high-performance Arm? Cortex?-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex?-M4 core features a Floating point unit (FPU) single precision which supports all Arm? single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32F479xx devices incorporate high-speed embedded memories (Flash memory up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers, a true random number generator (RNG), and a cryptographic acceleration cell. They also feature standard and advanced communication interfaces:

特性 Features

? Core: Arm? 32-bit Cortex?-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator?) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
? Memories
?Up to 2 MB of Flash memory organized into two banks allowing read-while-write
?Up to 384+4 KB of SRAM including 64 KB of CCM (core coupled memory) data RAM
?Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR, SDRAM, Flash NOR/NAND memories
?Dual-flash mode Quad-SPI interface
? Graphics:
?Chrom-ART Accelerator? (DMA2D), graphical hardware accelerator enabling enhanced graphical user interface with minimum CPU load
?LCD parallel interface, 8080/6800 modes
?LCD TFT controller supporting up to XGA resolution
?MIPI? DSI host controller supporting up to 720p 30Hz resolution
? Clock, reset and supply management
?1.7 V to 3.6 V application supply and I/Os
?POR, PDR, PVD and BOR
?4-to-26 MHz crystal oscillator
?Internal 16 MHz factory-trimmed RC (1% accuracy)
?32 kHz oscillator for RTC with calibration
?Internal 32 kHz RC with calibration
? Low power
?Sleep, Stop and Standby modes
?VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM
? 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
? 2×12-bit D/A converters
? General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
? Up to 17 timers: up to twelve 16-bit and two 32-bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. 2x watchdogs and SysTick timer
? Debug mode
?SWD & JTAG interfaces
?Cortex?-M4 Trace Macrocell?
? Up to 161 I/O ports with interrupt capability
?Up to 157 fast I/Os up to 90 MHz
?Up to 159 5 V-tolerant I/Os
? Up to 21 communication interfaces
?Up to 3 × I2C interfaces (SMBus/PMBus)
?Up to 4 USARTs and 4 UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control)
?Up to 6 SPIs (45 Mbits/s), 2 with muxed full-duplex I2S for audio class accuracy via internal audio PLL or external clock
?1 x SAI (serial audio interface)
?2 × CAN (2.0B Active)
?SDIO interface
? Advanced connectivity
?USB 2.0 full-speed device/host/OTG controller with on-chip PHY
?USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
?Dedicated USB power rail enabling on-chip PHYs operation throughout the entire MCU power supply range
?10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
? 8- to 14-bit parallel camera interface up to 54 Mbytes/s
? Cryptographic accelerator
?HW accelerator for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1, SHA-2) and HMAC
? True random number generator
? CRC calculation unit
? RTC: subsecond accuracy, hardware calendar
? 96-bit unique ID