STM32F050F6中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

描述 Description

The STM32F050xx family incorporates the high-performance ARM Cortex?-M0 32-bit RISC core operating at a 48 MHz maximum frequency, high-speed embedded memories (Flash memory up to 32 Kbytes and SRAM up to 4 Kbytes), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (one I2C, one SPI, one I2S, and one USART), one 12-bit ADC, up to five general-purpose 16-bit timers, a 32-bit timer and an advanced-control PWM timer.

特性 Features

■ Core: ARM 32-bit Cortex?-M0 CPU,

frequency up to 48 MHz

■ Memories

– 16 to 32 Kbytes of Flash memory

– 4 Kbytes of SRAM with HW parity checking

■ CRC calculation unit

■ Reset and supply management

– Voltage range: 2.0 V to 3.6 V

– Power-on/Power-down reset (POR/PDR)

– Programmable voltage detector (PVD)

– Low power modes: Sleep, Stop and

Standby

– VBAT supply for RTC and backup registers

■ Clock management

– 4 to 32 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– Internal 8 MHz RC with x6 PLL option

– Internal 40 kHz RC oscillator

■ Up to 39 fast I/Os

– All mappable on external interrupt vectors

– Up to 25 I/Os with 5 V tolerant capability

■ 5-channel DMA controller

■ 1 × 12-bit, 1.0 μs ADC (up to 10 channels)

– Conversion range: 0 to 3.6V

– Separate analog supply from 2.4 up to

3.6 V

■ Up to 9 timers

– 1 x 16-bit 7-channel advanced-control timer

for 6 channels PWM output, with deadtime

generation and emergency stop

– 1 x 32-bit and 1 x 16-bit timer, with up to 4

IC/OC, usable for IR control decoding

– 1 x 16-bit timer, with 2 IC/OC, 1 OCN,

deadtime generation and emergency stop

– 1 x 16-bit timer, with IC/OC and OCN,

deadtime generation, emergency stop and

modulator gate for IR control

– 1 x 16-bit timer with 1 IC/OC

– Independent and system watchdog timers

– SysTick timer: 24-bit downcounter

■ Calendar RTC with alarm and periodic wakeup

from Stop/Standby

■ Communication interfaces

– 1 x I2C interface; supporting Fast Mode

Plus (1 Mbit/s) with 20 mA current sink,

SMBus/PMBus, and wakeup from STOP

– 1 x USART supporting master synchronous

SPI and modem control; one with ISO7816

interface, LIN, IrDA capability auto baud

rate detection and wakeup feature

– 1 x SPI (18 Mbit/s) with 4 to 16

programmable bit frames, with I2S interface

multiplexed

■ Serial wire debug (SWD)

■ 96-bit unique ID

■ Extended temperature range: -40 to +105°C