SSTU32865

1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM

PHI

SSTU32865ET

1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM applications; \n\n?28-bit data register supporting DDR2\n\n?Fully compliant to JEDEC standard JESD82-9\n\n?Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (i.e. 2 x SSTU32864 or 2 x SSTU32866)\n\n?Parity checking function across 22 input data bits\n\n?Parity out signal\n\n?Controlled output impedance drivers enable optimal signal integrity and speed\n\n?Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation delay, 2.0 ns max. mass-switching)\n\n?Supports up to 450 MHz clock frequency of operation\n\n?Optimized pinout for high-density DDR2 module design\n\n?Chip-selects minimize power consumption by gating data outputs from changing state\n\n?Supports Stub Series Terminated Logic SSTL_18 data inputs\n\n?Differential clock (CK and CK) inputs\n\n?Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) switching levels on the control and RESET inputs\n\n?Single 1.8 V supply operation\n\n?Available in 160-ball 9 mm x 13 mm, 0.65 mm ball pitch TFBGA package\n\n\n;

Overview Archived content is no longer updated and is made available for historical reference only.\nThe SSTU32865 is a 1.8 V 28-bit 1:2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.\n The SSTU32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active-LOW).\n The SSTU32865 is packaged in a 160-ball, 12 x 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which-while requiring a minimum 9 mm x 13 mm of board space-allows for adequate signal routing and escape using conventional card technology.\n

恩XP

SSTU32865EG

1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM

PHI

SSTU32865ET

1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM

PHI

SSW-105-02-L-D-RA

SAMTEC/砷泰
汽車電子連接器

SAMTEC/砷泰