SN74HC377

具有時(shí)鐘使能端的八路 D 型觸發(fā)器; ? Wide Operating Voltage Range of 2 V to 6 V\n? Outputs Can Drive Up To 10 LSTTL Loads\n? Low Power Consumption, 80-μA Max ICC\n? Typical tpd = 12 ns\n? ±4-mA Output Drive at 5 V\n? Low Input Current of 1 μA Max\n? Eight Flip-Flops With Single-Rail Outputs\n? Clock Enable Latched to Avoid False Clocking\n? Applications Include: \n? Buffer/Storage Registers\n? Shift Registers\n? Pattern Generators;

These devices are positive-edge-triggered octal D-type flip-flops with an enable input. The ?HC377 devices are similar to the ?HC273 devices, but feature a latched clock-enable (CLKEN)\\ input instead of a common clear.\n\n Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse, if CLKEN\\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\\.

SN74HC377

OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

SN74HC377

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

SN74HC377

OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

SN74HC377

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

SN74HC377

OCTAL D-TYPE

SN74HC377A

具有時(shí)鐘使能端的八路 D 型觸發(fā)器;

SN74HC377DW

OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

SN74HC377DW

OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

SN74HC377DW

OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE