SN74ACT373

具有三態(tài)輸出的八路 D 類透明鎖存器; ? 4.5-V to 5.5-V VCC Operation\n? Inputs Accept Voltages to 5.5 V\n? Max tpd of 10 ns at 5 V\n? Inputs Are TTL-Voltage Compatible;

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.\n The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.\n A buffered output-enable (OE)\\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.\n (OE)\\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.\n To ensure the high-impedance state during power up or power down, (OE)\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.\n \n

SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN74ACT373-EP

具有三態(tài)輸出的增強(qiáng)型產(chǎn)品八路 D 類透明鎖存器; ? Controlled Baseline \n - One Assembly/Test Site, One Fabrication Site\n? Extended Temperature Performance of ?55°C to 125°C\n? Enhanced Diminishing Manufacturing Sources (DMS) Support\n? Enhanced Product-Change Notification\n? Qualification Pedigree\n? 4.5-V to 5.5-V VCC Operation\n? Inputs Accept Voltages to 5.5 V\n? Max tpd of 10 ns at 5 V\n? Inputs Are TTL-Voltage Compatible\nComponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.;

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.\n The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.\n A buffered output-enable (OE)\\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.\n OE\\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.\n To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.\n \n

SN74ACT373-EP

OCTAL D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

ControlledBaseline ?OneAssembly/TestSite,OneFabrication Site ExtendedTemperaturePerformanceof ?55°Cto125°C EnhancedDiminishingManufacturing Sources(DMS)Support EnhancedProduct-ChangeNotification QualificationPedigree? 4.5-Vto5.5-VVCCOperation InputsAcceptVoltages

SN74ACT373MDWREP

絲?。?a target="_blank" title="Marking" href="/sact373mep/marking.html">SACT373MEP；Package：SOIC；OCTAL D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

ControlledBaseline ?OneAssembly/TestSite,OneFabrication Site ExtendedTemperaturePerformanceof ?55°Cto125°C EnhancedDiminishingManufacturing Sources(DMS)Support EnhancedProduct-ChangeNotification QualificationPedigree? 4.5-Vto5.5-VVCCOperation InputsAcceptVoltages

SN74ACT373MDWREP.A

絲?。?a target="_blank" title="Marking" href="/sact373mep/marking.html">SACT373MEP；Package：SOIC；OCTAL D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

ControlledBaseline ?OneAssembly/TestSite,OneFabrication Site ExtendedTemperaturePerformanceof ?55°Cto125°C EnhancedDiminishingManufacturing Sources(DMS)Support EnhancedProduct-ChangeNotification QualificationPedigree? 4.5-Vto5.5-VVCCOperation InputsAcceptVoltages

SN74ACT373DB

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS