SMJ320C6701

軍用級 C67x 浮點 DSP - 陶瓷封裝; ? Highest Performance Floating-Point Digital Signal Processor (DSP) SMJ320C6701 \n? 7-, 6-ns Instruction Cycle Time\n? 140-, 167-MHz Clock Rate\n? Eight 32-Bit Instructions/Cycle\n? Up to 1 GFLOPS Performance\n? Pin-Compatible With ’C6201 Fixed-Point DSP\n \n? SMJ: QML Processing to MIL-PRF-38535\n? SM: Standard Processing\n? Operating Temperature Ranges \n? Extended (W) –55°C to 115°C\n? Extended (S) –40°C to 90°C\n \n? VelociTI? Advanced Very Long Instruction Word (VLIW) ’C67x CPU Core \n? Eight Highly Independent Functional Units: \n? Four ALUs (Floating- and Fixed-Point)\n? Two ALUs (Fixed-Point)\n? Two Multipliers (Floating- and Fixed-Point)\n \n? Load-Store Architecture With 32 32-Bit General-Purpose Registers\n? Instruction Packing Reduces Code Size\n? All Instructions Conditional\n \n? Instruction Set Features \n? Hardware Support for IEEE Single-Precision Instructions\n? Hardware Support for IEEE Double-Precision Instructions\n? Byte-Addressable (8-, 16-, 32-Bit Data)\n? 32-Bit Address Range\n? 8-Bit Overflow Protection\n? Saturation\n? Bit-Field Extract, Set, Clear\n? Bit-Counting\n? Normalization\n \n? 1M-Bit On-Chip SRAM \n? 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)\n? 512K-Bit Dual-Access Internal Data (64K Bytes)\n \n? 32-Bit External Memory Interface (EMIF) \n? Glueless Interface to Synchronous Memories: SDRAM and SBSRAM\n? Glueless Interface to Asynchronous Memories: SRAM and EPROM\n \n? Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel\n? 16-Bit Host-Port Interface (HPI) \n? Access to Entire Memory Map\n \n? Two Multichannel Buffered Serial Ports (McBSPs) \n? Direct Interface to T1/E1, MVIP, SCSA Framers\n? ST-Bus-Switching Compatible\n? Up to 256 Channels Each\n? AC97-Compatible\n? Serial-Peripheral-Interface (SPI) Compatible (Motorola?)\n \n? Two 32-Bit General-Purpose Timers\n? Flexible Phase-Locked-Loop (PLL) Clock Generator\n? IEEE-1149.1 (JTAG) Boundary-Scan-Compatible\n? 429-Pin Ceramic Ball Grid Array (CBGA) Package (GLP Suffix) and Land Grid Array (CLGA) Package (ZMB Suffix)\n? 0.18-μm/5-Level Metal Process \n? CMOS Technology\n \n? 3.3-V I/Os, 1.9-V Internal\n IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. VelociTI is a trademark of Texas Instruments Incorporated. Motorola is a trademark of Motorola, Inc. TI is a trademark of Texas Instruments Incorporated. Windows is a registered trademark of the Microsoft Corporation.;

The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (?C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI?), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the ?C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ?C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ?C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ?C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.\n\n The ?C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.\n\n The ?C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution.

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701-SP

航天級 C6701 浮點 DSP - 抗輻射 V 類、采用陶瓷封裝; ? Rad-Tolerant: 100-kRad (Si) TID\n? SEL Immune at 89MeV-cm2/mg LET Ions\n? QML-V Qualified, SMD 5962-98661\n? Highest-Performance Floating-Point Digital Signal Processor (DSP) SMJ320C6701 \n? 7-ns Instruction Cycle Time\n? 140-MHz Clock Rate\n? Eight 32-Bit Instructions/Cycle\n? Up to One GFLOPS Performance\n? Pin Compatible With ’C6201 Fixed-Point DSP\n \n? SMJ: QML Processing to MIL-PRF-38535\n? SM: Standard Processing\n? Operating Temperature Ranges \n? –55°C to 115°C\n? –55°C to 125°C\n \n? VelociTI Advanced Very Long Instruction Word (VLIW) ’C67x CPU Core \n? Eight Highly Independent Functional Units: \n? Four ALUs (Floating and Fixed Point)\n? Two ALUs (Fixed Point)\n? Two Multipliers (Floating and Fixed Point)\n \n? Load-Store Architecture With 32 32-Bit General-Purpose Registers\n? Instruction Packing Reduces Code Size\n? All Instructions Conditional\n \n? Instruction Set Features \n? Hardware Support for IEEE Single-Precision Instructions\n? Hardware Support for IEEE Double-Precision Instructions\n? Byte Addressable (8-/16-/32-Bit Data)\n? 32-Bit Address Range\n? 8-Bit Overflow Protection\n? Saturation\n? Bit-Field Extract, Set, Clear\n? Bit Counting\n? Normalization\n \n? 1M-Bit On-Chip SRAM \n? 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)\n? 512K-Bit Dual-Access Internal Data (64K Bytes)\n \n? 32-Bit External Memory Interface (EMIF) \n? Glueless Interface to Synchronous Memories: SDRAM and SBSRAM\n? Glueless Interface to Asynchronous Memories: SRAM and EPROM\n \n? Four-Channel Bootloading Direct Memory Access (DMA) Controller With Auxiliary Channel\n? 16-Bit Host-Port Interface (HPI) \n? Access to Entire Memory Map\n \n? Two Multichannel Buffered Serial Ports (McBSPs) \n? Direct Interface to T1/E1, MVIP, SCSA Framers\n? ST Bus Switching Compatible\n? Up to 256 Channels Each\n? AC97 Compatible\n? Serial Peripheral Interface (SPI) Compatible (Motorola)\n \n? Two 32-Bit General-Purpose Timers\n? Flexible Phase-Locked Loop (PLL) Clock Generator\n? IEEE Std 1149.1 (JTAG\n) Boundary Scan Compatible\n? 429-Pin Ceramic Ball Grid Array (CBGA/GLP) and Ceramic Land Grid Array (CLGA/ZMB) Package Types\n? 0.18-μm/5-Level Metal Process \n? CMOS Technology\n \n? 3.3-V I/Os, 1.9 V Internal\n? Engineering Evaluation (/EM) Samples are Available? \n \n IEEE Std 1149.1-1990 Test Access Port and Boundary Scan Architecture? These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life.;

The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 140 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.The ’C6701 has a complete set of development tools that includes a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

SMJ320C6701_07

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701_15

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701GLP

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701GLPW14

FLOATING - POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701GLPW14

FLOATING-POINT DIGITAL SIGNAL PROCESSOR