PLMX2624PAPSLASHEM中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

1 Features

? SMD 5962R2321001PXE

– Total ionizing dose 100Krad (ELDRS-free)

– Single event latch-up (SEL) immune up to

75MeV-cm2/mg

– Single event functional interrupt (SEFI) immune

up to 75MeV-cm2/mg

? Wide band frequency synthesizer : 5MHz to

28GHz output frequency

? –101dBc/Hz phase noise at 100kHz offset with

24GHz carrier

? 60fs RMS jitter at 24GHz (1kHz to 300MHz)

? Programmable output power

? PLL key specifications:

– Figure of merit: –236dBc/Hz

– Normalized 1/f noise: –129dBc/Hz

– Up to 200MHz phase detector frequency

? Synchronization of output phase across multiple

devices

? Independent mute pins for RFoutA and RFoutB

with 200ns mute/unmute time

? Support for SYSREF with 9ps resolution

programmable delay

? 3.3V single power supply operation

? Pin-mode: Pin configurable N divider and output

divider in Integer PLL mode

? 10 × 10mm2 64 lead QFP package

? Operating temperature range: –55°C to +125°C

? Supported by PLLatinum? Simulator design tool

2 Applications

? Space communications payload up to Ku/Ka

bands

? Space radar systems

? Command and Data handling system

? High-speed data converter clocking (supports

JESD204B/C)

? Local Oscillator for Mixer up to 28GHz frequency

3 Description

The LMX2624-SP is a high performance wideband

phase-locked loop (PLL) with integrated voltage

controlled oscillator (VCO) and voltage regulators that

can output any frequency from 5MHz and 28GHz.

The VCO on this device covers an entire octave so

the frequency coverage is complete down to 5MHz.

The high performance PLL with a figure of merit of

–236dBc/Hz and high phase detector frequency can

attain very low in-band noise and integrated jitter.

The LMX2624-SP allows users to synchronize the

output of multiple instances of the device. This

means that deterministic phase can be obtained

from a device in use cases including the one

with fractional engine or output divider enabled.

The device also adds support for either generating

or repeating SYSREF (compliant to JESD204B/C

standard), making the device designed for low-noise

clock source for high-speed data converters.

This device is fabricated in Texas Instruments'

advanced BiCMOS process and is available in a 64-

lead QFP plastic package.