MT48LC64M4A2集成電路（IC）的存儲(chǔ)器規(guī)格書PDF中文資料

General Description

The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Each of the x8’s 67,108,864-bit banks is organized as 8192 rows by 1024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 columns by 16 bits.

Features

? PC100- and PC133-compliant

? Fully synchronous; all signals registered on positive edge of system clock

? Internal, pipelined operation; column address can be changed every clock cycle

? Internal banks for hiding row access/precharge

? Programmable burst lengths: 1, 2, 4, 8, or full page

? Auto precharge, includes concurrent auto precharge and auto refresh modes

? Self refresh mode (not available on AT devices)

? Auto refresh

– 64ms, 8192-cycle refresh (commercial and industrial)

– 16ms, 8192-cycle refresh (automotive)

? LVTTL-compatible inputs and outputs

? Single 3.3V ±0.3V power supply