MT48LC4M32B2

SYNCHRONOUS DRAM

Features ?PC100-compliant ?Fullysynchronous;allsignalsregisteredonpositiveedgeofsystemclock ?Internalpipelinedoperation;columnaddresscanbechangedeveryclockcycle ?Internalbanksforhidingrowaccess/precharge ?Programmableburstlengths:1,2,4,8,orfull

MT48LC4M32B2

128Mb: x32 SDRAM MT48LC4M32B2 ??1 Meg x 32 x 4 Banks

MT48LC4M32B2

1 Meg x 32 x 4 Banks SDR SDRAM; ? PC100-compliant\n? Fully synchronous; all signals registered on positive edge of system clock\n? Internal pipelined operation; column address can be changed every clock cycle\n? Internal banks for hiding row access/precharge\n? Programmable burst lengths: 1, 2, 4, 8, or full page\n? Auto precharge, includes concurrent auto precharge and auto refresh modes\n? Self refresh mode (not available on AT devices)\n? Auto refresh\n– 64ms, 4096-cycle refresh (commercial and industrial)\n– 16ms, 4096-cycle refresh (automotive)\n? LVTTL-compatible inputs and outputs\n? Single 3.3V ±0.3V power supply\n? Supports CAS latency (CL) of 1, 2, and 3;

MT48LC4M32B2B51

SDR SDRAM MT48LC4M32B2 ??1 Meg x 32 x 4 Banks

Features ?PC100-compliant ?Fullysynchronous;allsignalsregisteredonpositiveedgeofsystemclock ?Internalpipelinedoperation;columnaddresscanbechangedeveryclockcycle ?Internalbanksforhidingrowaccess/precharge ?Programmableburstlengths:1,2,4,8,orfull

MT48LC4M32B2F51

SDR SDRAM MT48LC4M32B2 ??1 Meg x 32 x 4 Banks

Features ?PC100-compliant ?Fullysynchronous;allsignalsregisteredonpositiveedgeofsystemclock ?Internalpipelinedoperation;columnaddresscanbechangedeveryclockcycle ?Internalbanksforhidingrowaccess/precharge ?Programmableburstlengths:1,2,4,8,orfull

MT48LC4M32B2P

SDR SDRAM MT48LC4M32B2 ??1 Meg x 32 x 4 Banks

Features ?PC100-compliant ?Fullysynchronous;allsignalsregisteredonpositiveedgeofsystemclock ?Internalpipelinedoperation;columnaddresscanbechangedeveryclockcycle ?Internalbanksforhidingrowaccess/precharge ?Programmableburstlengths:1,2,4,8,orfull

MT48LC4M32B2P-7

SDR SDRAM MT48LC4M32B2 ??1 Meg x 32 x 4 Banks

Features ?PC100-compliant ?Fullysynchronous;allsignalsregisteredonpositiveedgeofsystemclock ?Internalpipelinedoperation;columnaddresscanbechangedeveryclockcycle ?Internalbanksforhidingrowaccess/precharge ?Programmableburstlengths:1,2,4,8,orfull

MT48LC4M32B2TG

SYNCHRONOUS DRAM

Features ?PC100-compliant ?Fullysynchronous;allsignalsregisteredonpositiveedgeofsystemclock ?Internalpipelinedoperation;columnaddresscanbechangedeveryclockcycle ?Internalbanksforhidingrowaccess/precharge ?Programmableburstlengths:1,2,4,8,orfull

MT48LC4M32B2TG

SDR SDRAM MT48LC4M32B2 ??1 Meg x 32 x 4 Banks

Features ?PC100-compliant ?Fullysynchronous;allsignalsregisteredonpositiveedgeofsystemclock ?Internalpipelinedoperation;columnaddresscanbechangedeveryclockcycle ?Internalbanksforhidingrowaccess/precharge ?Programmableburstlengths:1,2,4,8,orfull

MT48LC4M32B2B51

128Mb: x32 SDRAM MT48LC4M32B2 ??1 Meg x 32 x 4 Banks