MPC855TZQ50D4

PowerQUICC, 32 Bit Power Architecture SoC, 50MHz, CPM, ENET, ATM, HDLC, PCMCIA, 0 to 95C; Embedded MPC8xx core with 105 MIPS at 80 MHz (using Dhrystone 2.1)\n? 4-Kbyte Instruction Cache\n? 4-Kbyte Data Cache\n? 8 Kb Dual Port RAM\n? Instruction and Data MMUs\n? Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8, 16, and 32 Bits)\n? 32 Address Lines\n? Complete Static Design (0-80 MHz Operation)\n? Memory Controller (Eight Banks)\n? General-Purpose Timers\n? System Integration Unit (SIU)\n? Interrupts\n? Communications Processor Module (CPM)\n? Four Baud Rate Generators\n? One SCC (Serial Communication Controller)\n? Two SMCs (Serial Management Channels)\n? One SPI (Serial Peripheral Interface)\n? One I2C (Inter-Integrated Circuit) Port\n? Time-Slot Assigner\n? Parallel Interface Port\n? PCMCIA Interface\n? Low Power Support\n? Debug Interface\n? 3.3 V Operation with 3.3V I/O\n;

The MPC855T is a versatile one-chip integrated microprocessor and peripheral combination designed for lower cost access equipment that requires fast ethernet support capable of 100 Mbps. This member of the MPC860 PowerQUICC? family combines an MPC8xx core processor along with NXP? Semiconductors's own Communication Processor Module, a separate RISC engine specifically designed to offload communication tasks from the MPC8xx core.\nIt differs from existing PowerQUICC? family members in that the MPC855T features only one Serial Communications Controller instead of four. In addition, the MPC855T is manufactured in Our 0.32μ process technology allowing for 3.3 volt core operation and 3.3 volt I/O.\nThe MPC855T is packaged in a 357-pin BGA package and is footprint-compatible with existing MPC860 PowerQUICC designs. The MPC855T is also available at 50, 66, and 80 MHz and is supported by over 50 third party tool vendors.\n

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MPC855TZQ50D4

PowerQUICC??Family Hardware Specifications

MPC855TZQ50D4

Hardware Specifications

MPC855TZQ50D4R2

Hardware Specifications

MPC855TZQ50D4R2

PowerQUICC??Family Hardware Specifications