LPC4327JET100

32位ARM Cortex-M4/M0 MCU；高達1 MB的閃存和136 kB SRAM；以太網(wǎng)、兩個高速USB、LCD、EMC; ? Cortex-M4 Processor core? Arm Cortex-M4 processor, running at frequencies of up to 204 MHz\n? Arm Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions\n? Arm Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC)\n? Hardware floating-point unit\n? Non-maskable Interrupt (NMI) input\n? JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watchpoints\n? Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support\n? System tick timer\n? Cortex-M0 Processor core? Arm Cortex-M0 co-processor capable of off-loading the main Arm Cortex-M4application processor\n? Running at frequencies of up to 204 MHz\n? JTAG\n? Built-in NVIC\n? On-chip memory? Up to 1 MB on-chip dual bank flash memory with flash accelerator\n? 16 kB on-chip EEPROM data memory\n? 136 kB SRAM for code and data use\n? Multiple SRAM blocks with separate bus access. Two SRAM blocks can bepowered down individually\n? 64 kB ROM containing boot code and on-chip software drivers\n? 64 bit of general-purpose One-Time Programmable (OTP) memory\n? Configurable digital peripherals? Serial GPIO (SGPIO) interface\n? State Configurable Timer (SCT) subsystem on AHB\n? Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs andoutputs to event driven peripherals like the timers, SCT, and ADC0/1\n? Serial interfaces? Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second\n? One High-speed USB 2.0 Host/Device/OTG interface with DMA support andon-chip high-speed PHY\n? One High-speed USB 2.0 Host/Device interface with DMA support, on-chipfull-speed PHY and ULPI interface to external high-speed PHY\n? USB interface electrical test software included in ROM USB stack\n? One 550 UART with DMA support and full modem interface\n? Three 550 USARTs with DMA and synchronous mode support and a smart cardinterface conforming to ISO7816 specification. One USART with IrDA interface\n? Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controllerexcludes operation of all other peripherals connected to the same bus bridge\n? Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMAsupport\n? One SPI controller\n? One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/Opins conforming to the full I2C-bus specification. Supports data rates of up to1 Mbit/s\n? One standard I2C-bus interface with monitor mode and with standard I/O pins\n? Two I2S interfaces, each with DMA support and with one input and one output\n? Digital peripherals? External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,and SDRAM devices\n? LCD controller with DMA support and a programmable display resolution of up to1024 H x 768 V. Supports monochrome and color STN panels and TFT colorpanels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixelmapping. Available on parts LPC4357/53 only\n? Secure Digital Input Output (SD/MMC) card interface\n? Eight-channel General-Purpose DMA controller can access all memories on theAHB and all DMA-capable AHB slaves\n? Up to 164 General-Purpose Input/Output (GPIO) pins with configurablepull-up/pull-down resistors\n? GPIO registers are located on the AHB for fast access. GPIO ports have DMAsupport\n? Up to eight GPIO pins can be selected from all GPIO pins as edge and levelsensitive interrupt sources\n? Two GPIO group interrupt modules enable an interrupt based on a programmablepattern of input states of a group of GPIO pins\n? Four general-purpose timer/counters with capture and match capabilities\n? One motor control Pulse Width Modulator (PWM) for three-phase motor control\n? One Quadrature Encoder Interface (QEI)\n? Repetitive Interrupt timer (RI timer)\n? Windowed watchdog timer (WWDT)\n? Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytesof battery powered backup registers\n? Alarm timer; can be battery powered\n? Analog peripherals? One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s\n? Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.Up to eight input channels per ADC\n? Unique ID for each device\n? Clock generation unit? Crystal oscillator with an operating range of 1 MHz to 25 MHz\n? 12 MHz internal RC oscillator trimmed to 2 % accuracy over temperature andvoltage (1 % accuracy for Tamb = 0 °C to 85 °C)\n? Ultra-low power Real-Time Clock (RTC) crystal oscillator\n? Three PLLs allow CPU operation up to the maximum CPU rate without the need fora high-frequency crystal. The second PLL can be used with the High-speed USB,the third PLL can be used as audio PLL\n? Clock output\n? Power? Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for thecore supply and the RTC power domain\n? RTC power domain can be powered separately by a 3 V battery supply\n? Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deeppower-down\n? Processor wake-up from Sleep mode via wake-up interrupts from variousperipherals\n? Wake-up from Deep-sleep, Power-down, and Deep power-down modes viaexternal interrupts and interrupts generated by battery powered blocks in the RTCpower domain\n? Brownout detect with four separate thresholds for interrupt and forced reset\n? Power-On Reset (POR)\n? Available as LQFP208, LQFP144, LBGA256, or TFBGA100 packages\n;

The LPC435x/3x/2x/1x are Arm Cortex-M4 based microcontrollers for embeddedapplications which include an Arm Cortex-M0 coprocessor, up to 1 MB of flash and136 kB of on-chip SRAM, 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI),advanced configurable peripherals such as the State Configurable Timer (SCT) and theSerial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet,LCD, an external memory controller, and multiple digital and analog peripherals. TheLPC435x/3x/2x/1x operate at CPU frequencies of up to 204 MHz.\nThe Arm Cortex-M4 is a next generation 32-bit core that offers system enhancementssuch as low power consumption, enhanced debug features, and a high level of supportblock integration. The Arm Cortex-M4 CPU incorporates a 3-stage pipeline, uses aHarvard architecture with separate local instruction and data buses as well as a third busfor peripherals, and includes an internal prefetch unit that supports speculative branching.The Arm Cortex-M4 supports single-cycle digital signal processing and SIMDinstructions. A hardware floating-point unit is integrated in the core.\nThe Arm Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core whichis upward code- and tool-compatible with the Cortex-M4 core. The Cortex-M0coprocessor, designed as a replacement for existing 8/16-bit microcontrollers, offers up to204 MHz performance with a simple instruction set and reduced code size.\n