LPC1830FBD144

0kB Flash、200kB SRAM、以太網(wǎng)、LQFP144封裝; ? Arm Cortex-M3 processor, running at frequencies of up to 180 MHz\n? Arm Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions\n? Arm Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC)\n? Non-maskable Interrupt (NMI) input\n? JTAG and Serial Wire Debug\n? ETM and ETB support\n? System tick timer\n? 200 kB SRAM for code and data use\n? 32 kB ROM containing boot code and on-chip software drivers\n? Crystal oscillator with an operating range of 1 MHz to 25 MHz\n? 12 MHz internal RC oscillator trimmed to 1 % accuracy\n? Ultra-low power RTC crystal oscillator\n? Clock output\n? Two PLLs allow CPU operation up to the maximum CPU rate\n? Quad SPI Flash Interface with four lanes and data rates of up to 40 MB/s\n? 10/100T Ethernet MAC with RMII and MII interfaces and DMA support\n? One High-speed USB 2.0 Host/Device/OTG interface with DMA support\n? One High-speed USB 2.0 Host/Device interface with DMA support\n? Four 550 UARTs with DMA support: one UART with full modem interface\n? One UART with IrDA interface\n? One C_CAN 2.0B controller with one channel\n? Two SSP controllers with FIFO and multi-protocol support\n? One Fast-mode Plus I2C-bus interface with monitor mode\n? One standard I2C-bus interface with monitor mode and standard I/O pins\n? One I2S interface with DMA support and with one input and one output\n? External Memory Controller (EMC)\n? SD/MMC card interface\n? Eight-channel General-Purpose DMA (GPDMA) controller\n? Up to 83 General-Purpose Input/Output (GPIO) pins\n? GPIO registers are located on the AHB for fast access\n? State Configurable Timer (SCT) subsystem on AHB\n? Four general-purpose timer/counters with capture and match capabilities\n? One motor control PWM for three-phase motor control\n? One Quadrature Encoder Interface (QEI)\n? Repetitive Interrupt timer (RI timer)\n? Windowed watchdog timer\n? Ultra-low power Real-Time Clock (RTC) on separate power domain\n? Alarm timer; can be battery powered\n? One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s\n? Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s\n? Hardware-based AES security engine programmable through an on-chip API\n? Two 128-bit secure OTP memories for AES key storage and customer use\n? Unique ID for each device\n? Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip voltage regulator\n? RTC power domain can be powered separately by a 3 V battery supply\n? Four reduced power modes\n? Overdrive mode to increase CPU and bus clock frequency\n? Processor wake-up from Sleep mode via wake-up interrupts\n? Wake-up from Deep-sleep, Power-down, and Deep power-down modes\n? Brownout detect with four separate thresholds for interrupt and forced reset\n? Power-On Reset (POR)\n;

The LPC1830FBD144 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2.0 Host/OTG/Device and CAN 2.0B. Operating at speeds up to 180 MHz, the LPC1830 also features two new configurable peripherals: a SPI Flash Interface and a State Configurable Timer. All members of the series include a Wakeup Interrupt Controller allowing automatic wake from any priority interrupt as well as four reduced power modes: Sleep, Deep-Sleep, Power-Down, and Deep Power-Down.\n

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LPC1830FBD144

32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD, and external memory controller

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