CLA4607-085LF-EK1中文資料思佳訊數據手冊PDF規(guī)格書

Features

? Low thermal resistance: 55 °C/W

? Typical threshold level: +20 dBm

? Low capacitance: 0.30 pF

? Low profile, ultra-miniature QFN (3-pin, 2 x 2 mm) package

(MSL1, 260 °C per JEDEC J-STD-020)

Description

The CLA4607-085LF is a surface-mountable, low-capacitance

silicon PIN limiter diode designed as a shunt connected PIN diode

for high-power limiter applications from 10 MHz to over 6 GHz.

Maximum resistance at 10 mA is 2 Ω and maximum capacitance

at 38 V is 0.35 pF. The combination of low junction capacitance,

low parasitic inductance, low thermal resistance, and nominal

7 um I-region width, makes the CLA4607-085LF useful in large

signal limiter applications. The threshold level is +20 dBm,

nominal.

A block diagram of the CLA4607-085LF is shown in Figure 1. The

absolute maximum ratings of the CLA4607-085LF are provided in

Table 1. Electrical specifications are provided in Table 2.

Typical performance characteristics of the CLA4607-085LF are

provided in Table 3 and illustrated in Figures 4 and 5.