CDCLVP111

CDCLVP111-SP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

1Features ?DistributesOneDifferentialClockInputPair LVPECLto10DifferentialLVPECL ?FullyCompatibleWithLVECLandLVPECL ?SupportsaWideSupplyVoltageRangeFrom 2.375Vto3.8V ?SelectableClockInputThroughCLK_SEL ?Low-OutputSkew(Typical15ps)forClock- Distribution

CDCLVP111

具有可選輸入的 1:10 LVPECL 緩沖器; ? Distributes One Differential Clock Input PairLVPECL to 10 Differential LVPECL \n? Fully Compatible With LVECL and LVPECL\n? Supports a Wide Supply Voltage Range from 2.375 V to 3.8 V\n? Selectable Clock Input Through CLK_SEL\n? Low-Output Skew (Typical 15 ps) for Clock- Distribution Applications \n - Additive Jitter Less Than 1 ps\n? Propagation Delay Less Than 350 ps\n? Open Input Default State\n? LVDS, CML, SSTL Input Compatible\n? VBB Reference Voltage Output for Single-Ended Clocking\n? Available in a 32-Pin LQFP and QFN Package\n? Frequency Range From DC to 3.5 GHz\n? Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111\n? APPLICATIONS\n - Designed for Driving 50-Ω Transmission Lines\n? High Performance Clock Distribution\n \nAll other trademarks are the property of their respective owners;

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.\n The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed to GND through a 10-nF capacitor.\n However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.\n The CDCLVP111 device is characterized for operation from –40°C to 85°C.\n\n

CDCLVP111

LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER

CDCLVP111

Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

CDCLVP111

Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

CDCLVP111-EP

CDCLVP111-SP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

1Features ?DistributesOneDifferentialClockInputPair LVPECLto10DifferentialLVPECL ?FullyCompatibleWithLVECLandLVPECL ?SupportsaWideSupplyVoltageRangeFrom 2.375Vto3.8V ?SelectableClockInputThroughCLK_SEL ?Low-OutputSkew(Typical15ps)forClock- Distribution

CDCLVP111-EP

具有可選輸入的 HiRel、1:10 LVPECL 緩沖器; ? 將一個差分時鐘輸入對 LVPECL 分配至 10 個差分 LVPECL\n? 與低壓發(fā)射器耦合邏輯 (LVECL) 和 LVPECL 完全兼容\n? 支持 2.375V 至 3.8V 的寬電源電壓范圍\n? 通過 CLK_SEL 可選擇時鐘輸入\n? 針對時分應(yīng)用的低輸出偏斜（典型值 15ps） \n? 額外抖動少于 1ps\n? 傳播延遲少于 355ps\n? 開輸入缺省狀態(tài)\n? 低壓差分信令 (LVDS)，電流模式邏輯 (CML)，短截線串聯(lián)端接邏輯 (SSTL) 輸入兼容\n \n? 針對單端計時的 VBB基準電壓輸出\n? 采用 32 引腳薄型方形扁平 (LQFP) 封裝\n? 頻率范圍介于 DC 至 3.5GHz 之間\n? 與 MC100 系列 EP111，ES6111，LVEP111，PTN1111 引腳到引腳兼容;

CDCLVP111 時鐘驅(qū)動器使用最小的時分偏斜將 LVPECL 輸入的一個差分時鐘對 (CLK0，CLK1) 分頻為差分 LVPECL 時鐘 (Q0，Q9) 輸出的十個對。 CDCLVP111 可接受兩個時鐘源進入同一個輸入復(fù)用器。 CDCLVP111 專門設(shè)計用于驅(qū)動器 50? 傳輸線路。 當(dāng)一個輸出引腳不被使用時，建議將其保持在開狀態(tài)以減少功耗。 如果只使用差分對中的輸出引腳中的一個，那么其它輸出引腳必須被同樣地端接至 50?。 如果要求單端輸入運行，VBB基準電壓輸出被使用。 在這種情況下，VBB引腳應(yīng)該被連接至CLK0并由一個 10nF 電容器旁通至接地 (GND)。 然而，要實現(xiàn)高達 3.5GHz 的高速性能，強烈建議使用差分模式。 CDCLVP111 額定工作溫度范圍是 -55°C至 125°C。

CDCLVP111HFG/EM

絲印：CDCLVP111HFG/EM；Package：CFP；CDCLVP111-SP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

1Features ?DistributesOneDifferentialClockInputPair LVPECLto10DifferentialLVPECL ?FullyCompatibleWithLVECLandLVPECL ?SupportsaWideSupplyVoltageRangeFrom 2.375Vto3.8V ?SelectableClockInputThroughCLK_SEL ?Low-OutputSkew(Typical15ps)forClock- Distribution

CDCLVP111HFGSLASHEM

絲?。?a target="_blank" title="Marking" href="/cdclvp111hfg/em/marking.html">CDCLVP111HFG/EM；Package：CFP；CDCLVP111-SP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

1Features ?DistributesOneDifferentialClockInputPair LVPECLto10DifferentialLVPECL ?FullyCompatibleWithLVECLandLVPECL ?SupportsaWideSupplyVoltageRangeFrom 2.375Vto3.8V ?SelectableClockInputThroughCLK_SEL ?Low-OutputSkew(Typical15ps)forClock- Distribution

CDCLVP111HFGSLASHEM.Z

CDCLVP111-SP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver

1Features ?DistributesOneDifferentialClockInputPair LVPECLto10DifferentialLVPECL ?FullyCompatibleWithLVECLandLVPECL ?SupportsaWideSupplyVoltageRangeFrom 2.375Vto3.8V ?SelectableClockInputThroughCLK_SEL ?Low-OutputSkew(Typical15ps)forClock- Distribution