CD4024B

CMOS 7 級紋波進(jìn)位二進(jìn)制計數(shù)器/除法器; ? Medium-speed operation\n? Fully static operation\n? Buffered inputs and outputs\n? 100% tested for quiescent current at 20 V\n? Standardized, symmetrical output characteristics\n? Fully static operation\n? Common reset\n? 5-V, 10-V, and 15-V parametric ratings\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Noise margin (over full package-temperature range): ?????1 V at VDD = 5 V ?????2 V at VDD = 10 V ?????2.5 V at VDD = 15 V\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of 'B' Series CMOS Devices\"\n? Applications: \n - Control counters\n? Timers\n? Frequency dividers\n? Time-delay circuits\nCD4020B - 14 Stage CD4024B - 7 Stage CD4040B - 12 Stage;

CD4020B, CD4024B, and CD4040B are ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets thecounter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered.\n The CD4020B and CD4040B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4040B type also is supplied in 16-lead small-outline packages (M and M96 suffixes).\n The CD4024B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).\n \n

CD4024B

CMOS RIPPLE-CARRY BINARY COUNTER DIVIDERS

CD4024B

CMOS Ripple-Carry Binary Counter/Drivers

CD4024B

CMOS Ripple-Carry Binary Counter / Dividers

CD4024B

CD4000系列 邏輯芯片;

CD4024BC

7-Stage Ripple Carry Binary Counter

GeneralDescription TheCD4024BCisa7-stageripple-carrybinarycounter.Bufferedoutputsareexternallyavailablefromstages1through7.Thecounterisresettoitslogical“0”stagebyalogical“1”ontheresetinput.Thecounterisadvancedonecountonthenegativetransitionofeachc

CD4024BCM

7-Stage Ripple Carry Binary Counter

GeneralDescription TheCD4024BCisa7-stageripple-carrybinarycounter.Bufferedoutputsareexternallyavailablefromstages1through7.Thecounterisresettoitslogical“0”stagebyalogical“1”ontheresetinput.Thecounterisadvancedonecountonthenegativetransitionofeachc

CD4024BCN

7-Stage Ripple Carry Binary Counter

GeneralDescription TheCD4024BCisa7-stageripple-carrybinarycounter.Bufferedoutputsareexternallyavailablefromstages1through7.Thecounterisresettoitslogical“0”stagebyalogical“1”ontheresetinput.Thecounterisadvancedonecountonthenegativetransitionofeachc

CD4024BMS

CMOS Ripple-Carry Binary Counter/Dividers

Description CD4020BMS,CD4024BMS,andCD4040BMSareripplecarrybinarycounters.Allcounterstagesaremaster-slaveflip-flops.Thestateofacounteradvancesonecountonthenegativetransitionofeachinputpulse;ahighlevelontheRESETlineresetsthecountertoitsallzerosstate.S

CD4024BMS

CMOS Ripple-Carry Binary Counter/Divider; ? High Voltage Types (20V Rating) \n? Medium Speed Operation \n? Fully Static Operation \n? Buffered Inputs and Outputs \n? 100% Tested for Quiescent Current at 20V \n? Standardized Symmetrical Output Characteristics \n? Common Reset \n? 5V, 10V and 15V Parametric Ratings \n? Maximum Input Current of 1μa at 18V Over Full Package- Temperature Range; \n? 100nA at 18V and 25oC \n? Noise Margin (Over Full Package Temperature Range): \n? 1V at VDD = 5V \n? 2V at VDD = 10V \n? 2.5V at VDD = 15V \n? Meets All Requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications For Description Of 'B' Series CMOS Devices\"\n;

CD4020BMS - 14 Stage CD4024BMS - 7 Stage CD4040BMS - 12 Stage\nCD4020BMS, CD4024BMS, and CD4040BMS are ripplecarry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered.\nThe CD4020BMS, CD4024BMS and the CD4040BMS is supplied in these 14 lead outline packages:\n CD4020B CD4024B CD4040B Braze Seal DIP H4W H4Q H4X Frit Seal DIP H1F H1B H1F Ceramic Flatpack H6W H3W H6W