AM2634-Q1

AM263x Sitara? Microcontrollers

1Features ProcessorCores: ?Single,dual,andquad-coreArm?Cortex?-R5F MCUwitheachcorerunningupto400MHz –16KBI-cachewith64-bitECCperCPUcore –16KBD-cachewith32-bitECCperCPUcore –64KBTightly-CoupledMemory(TCM)with32- bitECCperCPUcore –LocksteporDual-c

AM2634-Q1

AM263x Sitara? Microcontrollers

1Features ProcessorCores: ?Single,dual,andquad-coreArm?Cortex?-R5F MCUwitheachcorerunningupto400MHz –16KBI-cachewith64-bitECCperCPUcore –16KBD-cachewith32-bitECCperCPUcore –64KBTightly-CoupledMemory(TCM)with32- bitECCperCPUcore –LocksteporDual-c

AM2634-Q1

具有實時控制、ASIL-D 功能安全和信息安全且頻率高達 400MHz 的四核 Arm? Cortex-R5F MCU; Processor Cores: \n? Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400?MHz \n? 16KB I-cache with 64-bit ECC per CPU core\n? 16KB D-cache with 32-bit ECC per CPU core\n? 64KB Tightly-Coupled Memory (TCM) with 32?bit ECC per each R5F core\n? Lock-step capability\n \n Memory Subsystem: \n? 2MB of On-Chip RAM (OCSRAM) \n? 4 Banks x 512KB\n? ECC error protection\n? Supports internal DMA engine\n \n Industrial Connectivity: \n? Dual-core Programmable Real-Time Unit and Industrial Communication Subsystem (PRU_ICSSM) enabling industrial communication protocols or motor control interfaces: \n? EtherCAT \n? PROFINET \n? EtherNET/IP?\n? IO-Link \n? Encoder Feedback\n? General Purpose Input/Output (GPIO)\n \n Sensing & Actuation: \n? Real-time Control Subsystem (CONTROLSS)\n? 20x Analog Comparators with programmable DAC reference (CMPSS)\n? 5x 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) \n? Up to 4 MSPS per ADC\n? 6 selectable inputs per ADC\n? Configurable as single-ended or differential inputs\n \n? 1x 12-bit DAC with buffered output\n? 32x enhanced High Resolution PWM modules (EHRPWM) \n? Extend the time resolution of the PWM compared to EPWM\n? Support single-ended or differential outputs\n \n? 10x enhanced Capture modules (ECAP)\n? 3x enhanced Quadrature Encoder Pulse modules (EQEP)\n? 2x Sigma-Delta Filter Modules (SDFM) each supporting up to 4 channels\n? Flexible signal multiplex crossbar (XBAR)\n System on Chip (SoC) Services and Architecture: \n? 1x EDMA to support data movement functions\n? Interprocessor communication modules \n? SPINLOCK module for synchronizing processes running on multiple cores\n? MAILBOX functionality implemented through CTRLMMR registers \n \n? Supports primary boot from the following interfaces: \n? UART\n? QSPI NOR Flash\n \n? Time sync support with time sync and compare event interrupt routers\n Functional Safety: \n? Enables design of systems with functional safety requirements \n? ECC or parity on calculation-critical memories\n? Built-In Self-Test (BIST) and fault-injection for CPU and on-chip RAM\n? Error Signal Module (ESM) with error pin\n? Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks \n \n? Functional Safety-Compliant targeted [Industrial] \n? Developed for functional safety applications\n? Documentation will be available to aid IEC 61508 functional safety system design\n? Systematic capability up to SIL-3 targeted\n? Hardware integrity up to SIL-3 targeted\n? Safety-related certification \n? IEC 61508 planned\n \n \n? Functional Safety-Compliant targeted [Automotive] \n? Developed for functional safety applications\n? Documentation will be available to aid ISO 26262 functional safety system design\n? Systematic capability up to ASIL-D targeted\n? Hardware integrity up to ASIL-D targeted\n? Safety-related certification \n? ISO 26262 planned\n \n \n? AEC-Q100 qualified for automotive applications\n Security: \n? Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA\n? Secure boot support \n? Device Take Over Protection\n? Hardware-enforced root-of-trust\n? Authenticated boot\n? S/W Anti-rollback Protection\n \n? Debug security \n? Debug of HS device allowed only with proper authentication\n? Provision to disable debug\n \n? Device ID and Key Management \n? Support for OTP Memory (FUSEROM) to store Root Keys & other security enabling fields\n? Separate EFUSE controllers and FUSE ROMs\n? Unique Device Public IDs\n \n? Memory Protection Units (MPU) \n? Arm? MPU present inside each Cortex?-R5F core\n \n? System MPU – present at various interfaces in the SoC (can be a firewall or MPU) \n? 8-16 Regions\n? Programmable (Privilege ID, Read/Write/Cachable, Start/End Address, Enable, Secure/Non Secure)\n \n \n \n? Cryptographic acceleration \n? Supports cryptographic cores \n? AES - 128/192/256 bits key sizes\n? SHA2 - 256/384/512 bit support\n? DRBG with Pseudo and True Random number generator\n? PKA (public key accelerator) to assist in RSA/ECC processing\n \n? DMA support\n \n High-Speed Interfaces: \n? Integrated Ethernet switch supporting two external ports \n? RMII(10/100) or RGMII (10/100/1000)\n? IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP\n? Clause 45 MDIO PHY management\n? Packet Classifier based on ALE engine with 512 classifiers\n? Priority based flow control\n? Packet size up to 2KB\n? Four CPU H/W interrupt Pacing\n? IP/UDP/TCP checksum offload in hardware\n \n Connectivity: \n? 6x Universal Asynchronous Receiver-Transmitters (UART)\n? 5x Serial Peripheral Interface (SPI) controllers\n? 5x Local Interconnect Network (LIN) ports\n? 4x Inter-Integrated Circuit (I2C) ports\n? 4x Modular Controller Area Network (MCAN) modules with CAN-FD support\n? 1x Quad Serial Peripheral Interface (QSPI)\n? Fast Serial Interface (FSI) with 4x receiver cores and 4x transmitter cores\n? Up to 140 General-Purpose I/O (GPIO) pins\n Media and Data Storage: \n? 1x Multi-Media Card/Secure Digital (MMC/SD) 4-bit interface\n? General-Purpose Memory Controller (GPMC) \n? 16-bit parallel data bus\n? 22-bit address bus\n? Up to 4MB addressable memory space\n? Integrated Error Location Module (ELM) support for error checking\n \n Technology / Package: \n? 45-nm technology\n? 15mm x 15mm, 0.8-mm pitch, 324-pin NFBGA;

AM2634-Q1

AM263x Sitara??Microcontrollers