ADSP-21MSP58BST-104中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The ADSP-21msp58 and ADSP-21msp59 Mixed-Signal Processors (MSProcessor? DSPs) are fully integrated, single-chip DSPs complete with a high performance analog front end. The ADSP-21msp58/59 Family is optimized for voice band applications such as Speech Compression, Speech Processing, Speech Recognition, Text-to Speech, and Speech-to-Text conversion.

FEATURES

38 ns Instruction Cycle Time (26 MIPS) from 13.00 MHz

Crystal

ADSP-2100 Family Code and Function Compatible with

New Instruction Set Enhanced for Bit Manipulation

Instructions, Multiplication Instructions, Biased

Rounding, and Global Interrupt Masking

2K 3 24 Words of On-Chip Program Memory RAM

2K 3 16 Words of On-Chip Data Memory RAM

4K 3 24 Words of On-Chip Program Memory ROM

(ADSP-21msp59 Only)

8-Bit Parallel Host Interface Port

Analog Interface Provides:

16-Bit Sigma-Delta ADC and DAC

Programmable Gain Stages

On-Chip Anti-Aliasing & Anti-Imaging Filters

8 kHz Sampling Frequency

65 dB ADC, SNR and THD

72 dB DAC, SNR and THD

425 mW Typical Power Dissipation @ 5.0 V @ 38 ns

<1 mW Powerdown Mode with 100 Cycle Recovery

Dual Purpose Program Memory for Both Instruction

and Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides:

Zero Overhead Looping

Conditional Instruction Execution

Two Double-Buffered Serial Ports with Companding

Hardware, One Serial Port (SPORT0) has Automatic

Data Buffering

Programmable 16-Bit Interval Timer with Prescaler

Programmable Wait State Generation

Automatic Booting of Internal Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

Through Host Interface Port

Stand-Alone ROM Execution (ADSP-21msp59 Only)

Single-Cycle Instruction Execution

Single-Cycle Context Switch

Multifunction Instructions

Three Edge- or Level-Sensitive External Interrupts

Low Power Dissipation in Standby Mode

100-Lead TQFP