ADN4604_V01中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

FEATURES

DC to 4.25 Gbps per port NRZ data rate

Programmable receive equalization

12 dB boost at 2 GHz

Compensates 40 inches of FR4 at 4.25 Gbps

Programmable transmit preemphasis/deemphasis

Up to 12 dB boost at 4.25 Gbps

Compensates 40 inches of FR4 at 4.25 Gbps

Low power: 130 mW per channel at 3.3 V (outputs enabled)

16 × 16, fully differential, nonblocking array

Double rank connection programming with dual connection maps

Low jitter, typically 20 ps

Flexible I/O supply range

DC- or ac-coupled differential CML inputs

Programmable CML output levels

Per-lane input P/N pair inversion for routing ease

50 Ω on-chip I/O termination

Supports 8b/10b, scrambled or uncoded NRZ data

Serial (I2C slave or SPI) control interface

100-lead TQFP, Pb-free package

APPLICATIONS

Fiber optic network switching

High speed serial backplane routing to OC-48 with FEC

XAUI: 10GBASE-KX4

Gigabit Ethernet over backplane: 1000BASE-KX

1×, 2×, and 4× Fibre Channel

InfiniBand?

Digital video (HDMI, DVI, DisplayPort, 3G-/HD-/SD-SDI)

Data storage networks