74HC390

Dual decade ripple counter

GENERALDESCRIPTION The74HC/HCT390arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?TwoBCDdecadeorbi-quinarycounters ?Onepackagecanbeconfiguredtodivide-

PHI

74HC390

DUAL DECADE RIPPLE COUNTER

DUALDECADERIPPLECOUNTER

74HC390

Dual decade ripple counter

1.Generaldescription The74HC390;74HCT390isadual4-bitdecaderipplecounterdividedintofourseparatelyclocked sections.Thecountershavetwodivide-by-2sectionsandtwodivide-by-5sections.Thesesections shareanasynchronousmasterresetinput(nMR)andcanbeusedinaBCDdecad

74HC390D

Dual decade ripple counter

GENERALDESCRIPTION The74HC/HCT390arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?TwoBCDdecadeorbi-quinarycounters ?Onepackagecanbeconfiguredtodivide-

PHI

74HC390D

Dual decade ripple counter

1.Generaldescription The74HC390;74HCT390isadual4-bitdecaderipplecounterdividedintofourseparatelyclocked sections.Thecountershavetwodivide-by-2sectionsandtwodivide-by-5sections.Thesesections shareanasynchronousmasterresetinput(nMR)andcanbeusedinaBCDdecad

74HC390D

Dual decade ripple counter; ? Input levels:? For 74HC390: CMOS level\n? For 74HCT390: TTL level\n\n? Two BCD decade or bi-quinary counters\n? One device can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100y\n? Two master reset inputs to clear each decade counter individually\n? Specified in compliance with JEDEC standard no. 7A\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Multiple package options\n? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decade or bi-quinary configuration. If master reset inputs 1MR and 2MR are used to clear all 8 bits of the counter simultaneously, numerous counting configurations are possible within one package. Section clocks nCP0 and nCP1, allow ripple counter or frequency division applications of divide-by-2, 4, 5, 10, 20, 25, 50 or 100.\n The HIGH-to-LOW transition of the clock inputs nCP0 and nCP1 trigger each section. For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide-by-5 section. For bi-quinary decade operation, the nQ3 output is connected to the nCP0 input and nQ0 becomes the decade output. A HIGH on the nMR input overrides the clocks and sets the four outputs LOW. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC390DB

Dual decade ripple counter

GENERALDESCRIPTION The74HC/HCT390arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?TwoBCDdecadeorbi-quinarycounters ?Onepackagecanbeconfiguredtodivide-

PHI

74HC390N

Dual decade ripple counter

GENERALDESCRIPTION The74HC/HCT390arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?TwoBCDdecadeorbi-quinarycounters ?Onepackagecanbeconfiguredtodivide-

PHI

74HC390PW

Dual decade ripple counter

GENERALDESCRIPTION The74HC/HCT390arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?TwoBCDdecadeorbi-quinarycounters ?Onepackagecanbeconfiguredtodivide-

PHI

74HC390PW

Dual decade ripple counter

1.Generaldescription The74HC390;74HCT390isadual4-bitdecaderipplecounterdividedintofourseparatelyclocked sections.Thecountershavetwodivide-by-2sectionsandtwodivide-by-5sections.Thesesections shareanasynchronousmasterresetinput(nMR)andcanbeusedinaBCDdecad