74AUP2G08DC

絲印：p08；Package：SOT765-1；Low-power dual 2-input AND gate

1.Generaldescription The74AUP2G08isadual2-inputANDgate.Schmitt-triggeractionatallinputsmakesthecircuit tolerantofslowerinputriseandfalltimes.Thisdeviceensuresverylowstaticanddynamicpower consumptionacrosstheentireVCCrangefrom0.8Vto3.6V. Thisdevicei

74AUP2G08DC

Low-power dual 2-input AND gate; ? Wide supply voltage range from 0.8 V to 3.6 V\n? High noise immunity\n? Complies with JEDEC standards:? JESD8-12 (0.8 V to 1.3 V)\n? JESD8-11 (0.9 V to 1.65 V)\n? JESD8-7 (1.2 V to 1.95 V)\n? JESD8-5 (1.8 V to 2.7 V)\n? JESD8-B (2.7 V to 3.6 V)\n\n? ESD protection:? HBM JESD22-A114F Class 3A exceeds 5000 V\n? MM JESD22-A115-A exceeds 200 V\n? CDM JESD22-C101E exceeds 1000 V\n\n? Low static power consumption; ICC = 0.9 μA (maximum)\n? Latch-up performance exceeds 100 mA per JESD78 Class II\n? Inputs accept voltages up to 3.6 V\n? Low noise overshoot and undershoot < 10 % of VCC\n? IOFF circuitry provides partial power-down mode operation\n? Multiple package options\n? Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃\n;

The 74AUP2G08 provides the dual 2-input AND function.\n Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.\n This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.\n

74AUP2G08DC

Low-power dual 2-input AND gate

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74AUP2G08DC

Low-power dual 2-input AND gate

PHI

74AUP2G08DC-Q100

Low-power dual 2-input AND gate; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? Wide supply voltage range from 0.8 V to 3.6 V\n? High noise immunity\n? CMOS low power dissipation\n? Low static power consumption; ICC = 0.9 μA (maximum)\n? Latch-up performance exceeds 100 mA per JESD78 Class II\n? Overvoltage tolerant inputs to 3.6 V\n? Low noise overshoot and undershoot < 10 % of VCC\n? IOFF circuitry provides partial Power-down mode operation\n? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B\n? Complies with JEDEC standards:? JESD8-12 (0.8 V to 1.3 V)\n? JESD8-11 (0.9 V to 1.65 V)\n? JESD8-7 (1.2 V to 1.95 V)\n? JESD8-5 (1.8 V to 2.7 V)\n? JESD8-B (2.7 V to 3.6 V)\n\n? ESD protection:? HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V\n? CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V\n\n;

The 74AUP2G08 is a dual 2-input AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.\n This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74AUP2G08DC,125

Package：8-VFSOP（0.091"，2.30mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 門和反相器 描述：IC GATE AND 2CH 2-INP 8VSSOP

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