28F320J5中文資料英特爾數(shù)據(jù)手冊PDF規(guī)格書

PRODUCT OVERVIEW

The Intel StrataFlash? memory family contains high-density memories organized as 8 Mbytes or 4 Mwords (64-Mbit) and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed as 8- or 16-bit words. The 64-Mbit device is organized as sixty-four 128-Kbyte (131,072 bytes) erase blocks while the 32-Mbits device contains thirty-two 128-Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable in-system. See the memory map in Figure 5.

■ High-Density Symmetrically-Blocked Architecture

- 64 128-Kbyte Erase Blocks (64 M)

- 32 128-Kbyte Erase Blocks (32 M)

■ 5 V VCC Operation

- 2.7 V I/O Capable

■ Configurable x8 or x16 I/O

■ 120 ns Read Access Time (32 M) 150 ns Read Access Time (64 M)

■ Enhanced Data Protection Features

- Absolute Protection with VPEN = GND

- Flexible Block Locking

- Block Erase/Program Lockout during Power Transitions

■ Industry-Standard Packaging

- μBGA* Package, SSOP and TSOP Packages (32 M)

■ Cross-Compatible Command Support

- Intel Basic Command Set

- Common Flash Interface

- Scaleable Command Set

■ 32-Byte Write Buffer

- 6 μs per Byte Effective Programming Time

■ 640,000 Total Erase Cycles (64 M) 320,000 Total Erase Cycles (32 M)

- 10,000 Erase Cycles per Block

■ Automation Suspend Options

- Block Erase Suspend to Read

- Block Erase Suspend to Program

■ System Performance Enhancements

- STS Status Output

■ Intel StrataFlash? Memory Flash Technology